(preliminary) pl611s-17 1.8v-3.3v picopll tm khz to mhz programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 01/04/07 page 1 features ? advanced programmable pll design for low- frequency (khz) input applications. ? input frequency: 10khz to 200mhz ? otp selectable ac/dc input coupling. ? accepts > 0.1v reference signal input voltage ? very low jitter and phase noise ? output frequency: o < 65mhz @ 1.8v operation o < 90mhz @ 2.5v operation o < 125mhz @ 3.3v operation ? disabled outputs programmable as hiz or active low. ? offered in tiny green /rohs compliant packages o 6-pin dfn (2.0mmx1.3mmx0.6mm) o 6-pin sc70 (2.3mmx2.25mmx1.0mm) o 6-pin sot23 (3.0mmx3.0mmx1.35mm) ? single 1.8v, 2.5v, or 3.3v 10% power supply ? operating temperature range from -40 c to 85 c description the pl611s-17 is a low-cost general purpose frequency synthesizer and a member of phaselinks picopll tm factory programmable quick turn clock (qtc) family. designed to fit in a small sot23, sc70, or dfn package for high performance, low power applications, the pl611s-17 accepts a low frequency (>10khz) reference input and generates up to 125mhz outputs with the best phase noise, jitter performance, and power consumption for handheld devices and notebook applications. in addition, one programmable i/o pin can be configured as output enable (oe), frequency switching (fsel), power down (pdb) input, or clk1 (f out , f ref , f ref /2) output. cascading the pl611s- 17 with other picopll ics can result in producing a ll required system clocks with specific savings in boa rd space, power consumption, and cost. package pin configuration block diagram charge pump vco fin programmable function phase detector r-counter (7-bit) m-counter (16-bit) p-counter (4-bit) f vco = f ref * (m/r) clk0 f out = f vco /2*p ref. programming logic oe, pdb, fsel, clk1 1 2 3 4 5 6 lf gnd clk0 oe, pdb, fsel, clk 1 vdd fin dfn dfn dfn dfn- -- -6 66 6l l l l ( (( (2 22 2. .. .0 00 0mmx mmx mmx mmx1 11 1. .. .3 33 3mmx mmx mmx mmx0 00 0. .. .6 66 6mm mmmm mm) )) ) sot sot sot sot23 2323 23- -- -6 66 6l l l l ( (( (3 33 3. .. .0 00 0mmx mmx mmx mmx3 33 3. .. .0 00 0mmx mmx mmx mmx1 11 1. .. .35 3535 35mm mmmm mm) )) ) fin vdd lf gnd clk0 oe, pdb, fsel, clk1 p p p p l l l l 6 6 6 6 1 1 1 1 1 1 1 1 s s s s - - - - 1 1 1 1 7 7 7 7 12 3 4 5 6 fin vdd gnd sc scsc sc70 7070 70- -- -6 66 6l l l l ( (( (2 22 2. .. .3 33 3mmx mmx mmx mmx2 22 2. .. .25 2525 25mmx mmx mmx mmx1 11 1. .. .0 00 0mm mmmm mm) )) ) lf clk0 p p p p l l l l 6 6 6 6 1 1 1 1 1 1 1 1 s s s s - - - - 1 1 1 1 7 7 7 7 oe, pdb, fsel, clk1 p p p p l l l l 6 6 6 6 1 1 1 1 1 1 1 1 s s s s - - - - 1 1 1 1 7 7 7 7 12 3 65 4
(preliminary) pl611s-17 1.8v-3.3v picopll tm khz to mhz programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 01/04/07 page 2 key programming parameters clk output frequency output drive strength programmable input/output f out = f ref * (m / r) /(2*p) where m=16 bit r= 7 bit p= 4 bit clk0 = f out , f ref or f ref / (2*p) clk1 = f ref , f ref /2, clk0 or clk0/2 three optional drive strengths to choose from: ? low: 4ma ? std: 8ma (default) ? high: 16ma one output pin can be configured as: ? oe - input ? fsel - input ? pdb - input ? clk1 C output ? hiz or active low disabled state package pin assignment pin # name sot pin# sc70 pin# dfn pin# type description vdd 1 2 3 p vdd connection. oe, pdb, fsel, clk1 2 1 2 i/o this programmable i/o pin can be configured as outp ut enable (oe) input, power down (pdb) input, frequency selector ( fsel) or clk1 clock output. this pin has an internal 10mn pull up resistor (oe, pdb & fsel only). the oe and pdb features can be programmed to allow the output to float (hi z), or to operate in the active low mode. state oe pdb fsel 0 disable clk power down mode frequency 2 1 (default) normal mode normal mode frequency 1 fin 3 3 1 i reference input pin. lf 4 4 6 i loop filter input pin. gnd 5 5 5 p gnd connection clk0 6 6 4 o programmable clock output
(preliminary) pl611s-17 1.8v-3.3v picopll tm khz to mhz programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 01/04/07 page 3 functional description pl611s-17 is a highly featured, very flexible, adva nced programmable pll design for high performance, low- power, small form-factor applications. the pl611s- 17 accepts a reference clock input of 10khz to 200m hz and is capable of producing two outputs up to 125mhz. thi s flexible design allows the pl611s-17 to deliver a ny pll generated frequency, f ref (ref clk) frequency or f ref /(2*p) to clk0 and/or clk1. some of the design fe atures of the pl611s-17 are mentioned below: pll programming the pll in the pl611s-17 is fully programmable. the pll is equipped with an 7-bit input frequency divider (r-counter), and an 16-bit vco frequency feedback loop divider (m-counter). the output of the pll is transferred to a 4-bit post vco divider (p- counter). the output frequency is determined by the following formula [f out = f ref * (m / r) / (2 * p) ]. clock output (clk0) clk0 is the main clock output. the pl611s-17 can also be programmed to provide a second clock output, clk1, on the programmable i/o pin (see oe/pdb/fsel/clk1 pin description below). the output of clk0 can be configured as the pll output (f vco /(2*p)), f ref (ref clk frequency) output, or f ref /(2*p) output. the output drive level can be programmed to low drive (4ma), standard drive (8ma) or high drive (16ma). the maximum output frequency is 125mhz. clock output (clk1) the clk1 feature allows the pl611s-17 to have an additional clock output. this output can be programmed to one of the following: f ref - reference ( ref clk ) frequency f ref / 2 clk0 clk0 / 2 output enable (oe) the output enable feature allows the user to enable and disable the clock output(s) by toggling the oe pin. the oe pin incorporates a 10mn pull up resist or giving a default condition of logic 1. the oe feature can be programmed to allow the output to float (hi z), or to operate in the activ e low mode. power-down control (pdb) the power down (pdb) feature allows the user to put the pl611s-17 into sleep mode. when activated (logic 0), pdb disables the pll, the oscillator circuitry, counters, and all other active circuitry . in power down mode the ic consumes <10ua of power. the pdb pin incorporates a 10mn pull up resistor giving a default condition of logic 1. the pdb feature can be programmed to allow the output to float (hi z), or to operate in the activ e low mode. frequency select (fsel) the frequency select (fsel) feature allows the pl611s-17 to switch between two pre-programmed outputs allowing the device on the fly frequency switching. the fsel pin incorporates a 10mn pull up resistor giving a default condition of logic 1 .
(preliminary) pl611s-17 1.8v-3.3v picopll tm khz to mhz programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 01/04/07 page 4 application recommendations for pl611s-17 pl611s-17 can accept a reference input >10khz and p roduce a clock output in the mhz range, as shown in the diagram 1, below. also, to save costs in consume r product system designs and for greater area optim ization, it is possible to use the xout of the rtc crystal (32. 768khz) as the reference input to the pl611s-17, as shown in diagram 2, below. diagram ?1? diagram ?2? note: an ac coupling cap may be required if rtc clo ck amplitude is too small. guidelines for external component selection for the optimum performance, an accurate external l oop filter capacitor must be selected. a general g uideline for selecting this component based on the input frequen cy is shown in the table below. input frequency capacitor value 3mhz ~ 200mhz 1.0nf 300khz ~ 10mhz 1.0nf 30khz ~ 1.0mhz 4.7nf 10khz ~ 100khz 47nf the optimal way to choose the value is using the fo llowing formula: c(nf) = 0.8 + m/280 where c = loop filter capacitor value (in nf) m = m counter value. provided by phaselink with de vice samples. notes: * find the closest commercially available value. va lues in the e12 range with 5% tolerance are accepta ble. * with possible m-counter values between 1 and 6553 6, the capacitor value is expected in the range 820 pf thru 220nf. 32.768 khz c1 c2 asic asic asic asic xin xout xin xout refin mhz clk (any frequency) 1.8~3.3v lf lfgnd oe, pdb fsel, clk1 p p p p l l l l 6 6 6 6 1 1 1 1 1 1 1 1 s s s s - - - - 1 1 1 1 7 7 7 7 12 3 65 4 refin mhz clk (any frequency) 1.8~3.3v lf lfgnd oe, pdb fsel, clk1 p p p p l l l l 6 6 6 6 1 1 1 1 1 1 1 1 s s s s - - - - 1 1 1 1 7 7 7 7 12 3 65 4
(preliminary) pl611s-17 1.8v-3.3v picopll tm khz to mhz programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 01/04/07 page 5 electrical specifications absolute maximum ratings parameters symbol min. max. units supply voltage range v dd -0.5 7 v input voltage range v i -0.5 v dd +0.5 v output voltage range v o -0.5 v dd +0.5 v soldering temperature (green package) 260 c data retention @ 85 c 10 year storage temperature t s -65 150 c ambient operating temperature* -40 85 c exposure of the device under conditions beyond the limits specified by maximum ratings for extended pe riods may cause permanent damage to the device and affect product reliability. these conditions r epresent a stress rating only, and functional opera tions of the device at these or any other condition s above the operational limits noted in this specification is not implied. *operating temperature is guarante ed by design. parts are tested to commercial grade only. ac specifications parameters conditions min. typ. max. units @ v dd =3.3v 200 @ v dd =2.5v 166 input (fin) frequency @ v dd =1.8v 10khz 133 mhz input (fin) signal amplitude internally ac/dc coupl ed (high frequency) 0.9 v dd vpp input (fin) signal amplitude internally ac/dc coupled (low frequency) 3.3v < 50mhz, 2.5v < 40mhz, 1.8v < 15mhz 0.1 v dd v pp @ v dd =3.3v 125 @ v dd =2.5v 90 output frequency @ v dd =1.8v 65 mhz settling time at power-up (after v dd increases over 1.62v) 2 ms oe function; ta=25o c, 15pf load 10 ns output enable time pdb function; ta=25o c, 15pf load 2 ms output rise time 15pf load, 10/90% v dd , high drive, 3.3v 1.2 1.7 ns output fall time 15pf load, 90/10% v dd , high drive, 3.3v 1.2 1.7 ns duty cycle v dd /2 45 50 55 % period jitter, pk-to-pk* (measured from 10,000 samples) with capacitive decoupling between v dd and gnd. 70 ps * note: jitter performance depends on the programmi ng parameters.
(preliminary) pl611s-17 1.8v-3.3v picopll tm khz to mhz programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 01/04/07 page 6 dc specifications parameters symbol conditions min. typ. max. units supply current, dynamic, with loaded cmos outputs i dd @ v dd =3.3v,30mhz, load=15pf 6.0 ma supply current, dynamic, with loaded cmos outputs i dd @ v dd =2.5v,30mhz, load=15pf 3.9 ma supply current, dynamic with loaded cmos outputs i dd @ v dd =1.8v,30mhz, load=5pf 2.1* ma operating voltage v dd 1.62 3.63 v output low voltage v ol i ol = +4ma standard drive 0.4 v output high voltage v oh i oh = -4ma standard drive v dd C 0.4 v output current, low drive i osd v ol = 0.4v, v oh = 2.4v 4 ma output current, standard drive i osd v ol = 0.4v, v oh = 2.4v 8 ma output current, high drive i ohd v ol = 0.4v, v oh = 2.4v 16 ma
(preliminary) pl611s-17 1.8v-3.3v picopll tm khz to mhz programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 01/04/07 page 7 pcb layout considerations for performance optimizat ion the following guidelines are to assist you with a p erformance optimized pcb design: - keep all the pcb traces to pl611s-17 as short as possible, as well as keeping all other traces as fa r away from it as possible. - when a reference input clock is generated from a crystal (see diagram above), place the pl611s-17 fin as close as possible to the xout crystal pi n. this will reduce the cross-talk between the referen ce input and the other signals. - place the loop filter (lf) components as close to the package pin of pl611s-17 as possible. - place a 0.01uf~0.1uf decoupling capacitor between vdd and gnd, on the component side of the pcb, close to the vdd pin. it is not recommended to place this component on the backside of the pcb. going through vias will reduc e the signal integrity, causing additional jitter and phase noise. - it is highly recommended to keep the vdd and gnd traces as short as possible. - when connecting long traces (> 1 inch) to a cmos output, it is important to design the traces as a transmission line or stripline, to avoid reflecti ons or ringing. in this case, the cmos output needs to be matched to the trace impedance. usually striplines are designed for 50n impedance and cmos outputs usually have lower than 50n impedance so matching can be achieved by adding a resistor in series with the cmos output pin to the stripline trace. - please contact phaselink for the application note on how to design outputs driving long traces or the gerber files for the pl611s-17 layout.
(preliminary) pl611s-17 1.8v-3.3v picopll tm khz to mhz programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 01/04/07 page 8 d e bottom view d1 b e e1 l a3 a a1 pin 6 id chamfer pin1 dot top view package drawings ( green package compliant) sot23-6 l sc70-6l dfn-6l dimension in mm symbol min. max. a 1.05 1.35 a1 0.05 0.15 a2 1.00 1.20 b 0.30 0.50 c 0.08 0.20 d 2.80 3.00 e 1.50 1.70 h 2.60 3.00 l 0.35 0.55 e 0.95 bsc dimension in mm symbol min. max. a 0.80 1.00 a1 0.00 0.09 a2 0.80 0.91 b 0.15 0.30 c 0.08 0.25 d 1.85 2.25 e 1.15 1.35 h 2.00 2.30 l 0.21 0.41 e 0.65bsc dimension in mm symbol min. max. a 0.50 0.60 a1 0.00 0.05 a3 0.152 0.152 b 0.15 0.25 e 0.40bsc d 1.25 1.35 e 1.95 2.05 d1 0.75 0.85 e1 0.95 1.05 l 0.20 0.30 c l a2 e h d a1 e b a pin1 dot c l a2 e h d a1 e b a pin1 dot
(preliminary) pl611s-17 1.8v-3.3v picopll tm khz to mhz programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 01/04/07 page 9 ordering information ( green package compliant) for part ordering, please contact our sales departm ent: 47745 fremont blvd., fremont, ca 94538, usa tel: (510) 492-0990 fax: (510) 492-0991 part number the order number for this device is a combination of the following: part number, package type and operating temperature range pl611s -17-xxx x x x part/order number marking ? package option pl611s-17-xxxgc-r xxx 6-pin dfn (tape and reel) pl611s-17-xxxuc-r xxx 6-pin sc70 (tape and reel) pl611s-17-xxxtc-r 17xxx 6-pin sot23 (tape and reel) ? note: xxx designates marking identifier that coul d be independent of the part number. phaselink corporation, reserves the right to make c hanges in its products or specifications, or both a t any time without notice. the information furnished by phaselink is believed to be accurate a nd reliable. however, phaselink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any lo ss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : phaselinks products are not authorized for use a s critical components in life support devices or sy stems without the express written approval of the president of phasel ink corporation. solder reflow profile available at www.phaselink.com/qa/solderinggreen.pdf part number temperature c=commercial i=industrial package type g=dfn-6l u=sc70-6l t=sot-6l 3 digit id code * (will be assigned at programming time) n one= tube r=tape and reel
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